An active matrix display apparatus comprises a panel having gate lines in a form of rows, signal lines in a form of columns, and pixels arranged in a form of a matrix at intersections of the gate lines and the signal lines. A thin film transistor (TFT), for example, is formed as an active element in each of the pixels. The display apparatus further includes a vertical driving circuit and a horizontal driving circuit. The vertical driving circuit is connected to each of the gate lines, and sequentially selects rows of the pixels. The horizontal driving circuit is connected to each of the signal lines, and sequentially writes a video signal to pixels of a selected row. At this time, the horizontal driving circuit in a dot-sequential driving system writes the video signal to the pixels of the selected row on a dot-sequential basis.
In the active matrix display apparatus, there is parasitic capacitance between source/drain electrodes of TFTs and signal lines. This parasitic capacitance may cause a potential change at the time of writing the video signal through a certain signal line to jump into an adjacent signal line, resulting in a picture defect such as a vertical streak or the like. This vertical streak defect is conspicuous especially when a checkered pattern is displayed in a line reversal driving system. Alternatively, a vertical streak tends to occur when a horizontal line having a thickness of one dot (one pixel) is displayed in a dot line reversal driving system.
In order to prevent the jump of the video signal between the signal lines, so-called divided sample and hold driving has been proposed, which is disclosed in Japanese Patent Laid-Open No. 2000-267616, for example. The divided sample and hold system separates an input video signal into two systems, and writes the video signal on a dot-sequential basis while overlapping the video signals in the two systems for pixels adjacent to each other.
FIG. 7 is a schematic diagram showing an example of a display apparatus using the above-mentioned divided sample and hold driving. As shown in FIG. 7, the display apparatus comprises a panel including gate lines 113 in a form of rows, signal lines 112 in a form of columns, pixels 111 arranged in a form of a matrix at intersections of the gate lines 113 and the signal lines 112, and two video lines 125 and 126 for supplying video signals Video 1 and Video 2 separated in two systems in predetermined phase relation. A sampling switch group 123 is disposed so as to correspond to each of the signal lines 112, and is connected between each of the two video lines and the signal lines with two signal lines as a unit. Specifically, a first signal line is connected to one video line 125 via a sampling switch, and a second signal line is similarly connected to the other video line 126 via a sampling switch. Thereafter, a third and succeeding signal lines are alternately connected to the two video lines 125 and 126 via sampling switches. Also formed on the panel are a vertical driving circuit 116 and a horizontal driving circuit 117. The vertical driving circuit 116 is connected to each of the gate lines 113 to sequentially select rows of the pixels 111. In other words, the pixels 111 arranged in the form of a matrix are sequentially selected in units of a row. The horizontal driving circuit 117 operates on the basis of a clock signal having a predetermined cycle. The horizontal driving circuit 117 sequentially generates sampling pulses A, B, C, D, . . . of which pulses supplied to switches connected to the same video line among the switches of the sampling switch group 123 do not overlap each other and pulses supplied to adjacent switches overlap each other, and then sequentially drives the switches for opening and closing thereof. The video signals are thereby written to pixels 111 of a selected row on the dot-sequential basis. The display apparatus further includes a clock generating circuit 189. The clock generating circuit 189 supplies a start pulse HST as well as a clock signal HCK serving as a basis for operation of the horizontal driving circuit 117. The horizontal driving circuit 117 comprises a multistage-connected shift register (S/R) 121. The shift register 121 sequentially transfers the start pulse HST in response to the clock signal HCK and thereby sequentially generates the above-mentioned sampling pulses A, B, C, D . . . .
Operation of the conventional display apparatus shown in FIG. 7 will be briefly described with reference to a waveform chart of FIG. 8. As described above, the horizontal driving circuit operates in response to the clock signal HCK, and generates the sampling pulses A, B, C, D . . . by sequentially transferring the start pulse HST. As is clear from FIG. 8, sampling pulses between adjacent signal lines overlap each other. Specifically, the sampling pulse A corresponding to the first signal line overlaps the sampling pulse B corresponding to the second signal line. Similarly, the sampling pulse B corresponding to the second signal line overlaps the sampling pulse C corresponding to the third signal line. Since the signal lines adjacent to each other are supplied with the video signals from the separate video lines, the overlap does not present a problem. The sampling pulses supplied to the sampling switches of the signal lines adjacent to each other are generated so as to overlap each other, whereby a conventional problem of a vertical streak defect can be prevented. Specifically, even when there is parasitic capacitance between the source/drain electrodes of the pixel transistors and the signal lines and a potential change in a certain signal line jumps into an adjacent signal line via the parasitic capacitance, the signal line is at low impedance because of overlap sampling, and is therefore not affected by the jump of the video signal.
In the example shown in FIG. 8, a signal potential Sig1 is sampled and held in the corresponding first signal line in response to the sampling pulse A. Then, a signal potential Sig2 is sampled and held in the second signal line in response to the sampling pulse B. At this time, a potential change occurs in the second signal line. This potential change also jumps into the first signal line via the parasitic capacitance. At this time, since the sampling switch corresponding to the first signal line is still opened, the first signal line is at a low impedance and is therefore not affected by the signal jump.
FIG. 9 schematically shows timing of the sampling of the video signals for the signal lines and change in potential of the video lines. Basically, sampling pulses supplied to the sampling switches connected to the same video line are generated so as not to overlap each other. For example, the first signal line and the third signal line are connected to the same video line. Circuit design is thus made such that the sampling pulse A and the sampling pulse C do not overlap each other in principle. In practice, however, a delay is caused by wiring resistance, parasitic capacitance and the like, and waveforms of the sampling pulse A and the sampling pulse C are rounded in a pulse transmission process. As a result, the sampling pulse A and the sampling pulse C partially overlap each other. In such a state, when the sampling pulse C rises, the corresponding sampling switch is opened, and charge/discharge occurs in the signal line, thus resulting in a potential swing in the video signal Video 1 on the video line, as indicated by a solid arrow. At this time, because the preceding sampling pulse A has not completely fallen yet, the potential swing (charge/discharge noise) on the video line is picked up, as indicated by a dotted arrow. This results in variation in the potential sampled and supplied to the signal line, and hence a vertical streak on the screen, which degrades picture quality. Further, such an interference of the video signal between signal lines connected to the same video line may cause a ghost or the like on the screen.